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| author |   thmsdt <thomas.kulik@telekom.de> | 2022-03-17 11:17:14 +0100 |
|---|---|---|
| committer | thmsdt <thomas.kulik@telekom.de> | 2022-03-17 11:18:22 +0100 |
| commit | 39f529436a6d0c8ffd357219a7418eb8326307dc (patch) | |
| tree | f04bd0b1d84f4acd492c51599e7b514729ed4821 /docs/guides/onap-user/design/index.rst | |
| parent | 1cc31c35e59dd9e19869ce2f32b626a35aeb4803 (diff) | |
cleanup documentation (not branched, unmaintained) #4
Issue-ID: DOC-782
Signed-off-by: thmsdt <thomas.kulik@telekom.de>
Change-Id: I95bb112bcb0a8b52fe18aca5f62924e3d69226a1
Diffstat (limited to 'docs/guides/onap-user/design/index.rst')
| -rw-r--r-- | docs/guides/onap-user/design/index.rst | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/docs/guides/onap-user/design/index.rst b/docs/guides/onap-user/design/index.rst index 0100c0d98..b42d02224 100644 --- a/docs/guides/onap-user/design/index.rst +++ b/docs/guides/onap-user/design/index.rst @@ -72,12 +72,6 @@ Onboarding, Design and Distribution process. provides some policy models that are implemented and pre-loaded when installing ONAP. -**VNF LifeCycle Command templating** - APPC Controller Design Tool (CDT) is used for self-service onboarding of - VNFs. VNF owners can create templates and other artifacts for APPC - Configure command (used to apply a post-instantiation configuration) - as well as other life cycle commands. - **Workflow Design** The purpose of the Workflow Designer is to enable designers to define or modify workflows to support Service/Resource change management scenarios @@ -102,9 +96,9 @@ The following sections focus on the different Design steps: VF Creation and Testing <./vfcreation/index.rst> Service Design <./service-design/index.rst> Service Distribution <./service-distribution/index.rst> - VNF parameter resolution Design <./parameter_resolution/index.rst> + VNF Parameter Resolution Design <./parameter_resolution/index.rst> Control Loop Design <./control-loop/index.rst> - Instructions for control loop design <./control-loop-design-steps/cl_design_instructions.rst> + Instructions for Control Loop Design <./control-loop-design-steps/cl_design_instructions.rst> The following section provide links to the projects: |