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| author |   Huang Haibin <haibin.huang@intel.com> | 2018-10-18 15:35:33 +0800 |
|---|---|---|
| committer |   Gary Wu <gary.i.wu@huawei.com> | 2018-10-18 15:22:45 +0000 |
| commit | 8332cbbf4e68f68a5927403be646c26ab9667fae (patch) | |
| tree | b23d31b8a917204c37075faef83df9d285fb8cfa /tosca/vCPE/vgw/MainServiceTemplate_sriov.yaml | |
| parent | 1e1a8bfbc608f7f144c7fbdfc7e7bb1281dd149e (diff) | |
Fix Tosca csar with error variable
a. We don't define oam_private_net_cidr but define onap_private_net_cidr
b. sdnc_ip change to sdnc_ip_addr
c. define mr_ip_port for infra
Change-Id: If8f1b3062d5f1c78881967c24b8d8dd32e197781
Issue-ID: INT-693
Signed-off-by: Huang Haibin <haibin.huang@intel.com>
Diffstat (limited to 'tosca/vCPE/vgw/MainServiceTemplate_sriov.yaml')
| -rw-r--r-- | tosca/vCPE/vgw/MainServiceTemplate_sriov.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tosca/vCPE/vgw/MainServiceTemplate_sriov.yaml b/tosca/vCPE/vgw/MainServiceTemplate_sriov.yaml index f8a6adda..94ca7316 100644 --- a/tosca/vCPE/vgw/MainServiceTemplate_sriov.yaml +++ b/tosca/vCPE/vgw/MainServiceTemplate_sriov.yaml @@ -318,7 +318,7 @@ topology_template: vf_module_id: { get_input: vf_module_id } mux_gw_private_net_ipaddr: { get_input: vgw_private_ip_0 } oam_ipaddr: { get_input: vgw_private_ip_1 } - oam_cidr: { get_input: oam_private_net_cidr } + oam_cidr: { get_input: onap_private_net_cidr } cpe_public_net_cidr: { get_input: cpe_public_net_cidr } mux_gw_private_net_cidr: { get_input: mux_gw_private_net_cidr } mux_ip_addr: { get_input: mux_ip_addr } |