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| author |   Vijay Venkatesh Kumar <vv770d@att.com> | 2020-02-21 19:22:38 +0000 |
|---|---|---|
| committer |   Gerrit Code Review <gerrit@onap.org> | 2020-02-21 19:22:38 +0000 |
| commit | 729478d078e7570824472d02ff0d4e115cb33144 (patch) | |
| tree | 8abb1c40fb158e27cf1175ff3ed19bc8a0a4b437 /docs/sections/services/son-handler/son_handler_overview.rst | |
| parent | cc673dc6fef15973fa48cc55a69c64291ed5e92b (diff) | |
| parent | bb94cb7d7a20e62da9eed8b07c3a82fd28bd38eb (diff) | |
Merge "DL-Handler Doc"
Diffstat (limited to 'docs/sections/services/son-handler/son_handler_overview.rst')
| -rw-r--r-- | docs/sections/services/son-handler/son_handler_overview.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/sections/services/son-handler/son_handler_overview.rst b/docs/sections/services/son-handler/son_handler_overview.rst index 23abbaa7..41dbd844 100644 --- a/docs/sections/services/son-handler/son_handler_overview.rst +++ b/docs/sections/services/son-handler/son_handler_overview.rst @@ -24,7 +24,7 @@ The core logic is implemented as 3 threads - main thread, child thread(s) for ha (b) Autonomously taking actions for ANR updates
(c) Preparing the message contents required by SDN-R to re-configure the RAN nodes with PCI/ANR updates
-The logic may not be 100% fool-proof (i.e., cover all possible scenarios and boundary-counditions as in real field deployments), as well as the most efficient one. An attempt has been made to balance the usefulness for a PoC versus the complexity of handling all possible scenarios. It is intended to provide a good base for the community/users to enhance it further as required.
+The logic may not be 100% fool-proof (i.e., cover all possible scenarios and boundary-conditions as in real field deployments), as well as the most efficient one. An attempt has been made to balance the usefulness for a PoC versus the complexity of handling all possible scenarios. It is intended to provide a good base for the community/users to enhance it further as required.
The details of the state machines of all the threads in the core logic are available in https://wiki.onap.org/pages/viewpage.action?pageId=56131985.
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